This is the gSheet implementation of IDesignSpec - a popular tool for creating Control and Status Register maps for IP and SoCs.
IDesignSpec (IDS) is an engineering tool that allows a chip or system designer to create the design specification once and automatically generate all possible views from it, without re-write or any duplication. Designs created using IDS are Correct-By-Construction. IDS makes the design process efficient, and cost effective.
IDS now has a Google Sheet front-end called IDesignSpec gSheets. It is an add-on to Google Sheets that enables you to create Hardware Functional specification with embedded templates that can be transformed into code such as Verilog, VHDL, UVM, C++ header files, IP-XACT etc.